0.1-1.5 GHz All-Digital Delay Locked Loop
An all-digital wide-range phase-inversion delay-locked loop (PIDLL) with a high-resolution duty-cycle corrector (DCC) for high-speed and low-power AP, SoC and memory devices is presented. The proposed PIDLL utilizes a new phase inversion scheme to reduce the total number of delay elements (DEs) in the digitally control..
KU386H0501 | 2014-04-07