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BCD1370_PLL
It was designed using Samsung Foundry's BCD1370 process.
PLLs have been developed as phase locked loops in a variety of applications.
The PLL generates 60~180MHz clock referenced at 8~20MHz.
The output clock frequency is selected by the resister P, M, S
PLL output frequency PLLOUT = FIN / Pdiv_val * Mdiv_val / Sdiv..
KC022H1150 | 2022-09-21
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PLL 4G
The PLL 4G IP is Clock Generator PLL that Widely programmable fractional-N delta sigma frequency synthesizer.
The PLL 4G IP additionally uses an LVT device to provide clocks up to 4.5 GHz.
It contains a 1-64 divider at the reference clock input, a 16-2000(Integer Mode) divider in the internal feedback path, and a 1-..
KC639H1110 | 2021-11-10
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PLL 3G
The PLL 3G IP is Clock Generator PLL that Widely programmable fractional-N delta sigma frequency synthesizer.
PLL 3G uses only RVT device to provide a clock with a maximum frequency of 3.5GHz.
It contains a 1-64 divider at the reference clock input, a 16-2000(Integer Mode) divider in the internal feedback path, and ..
KC639H1109 | 2021-11-10
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PLL 60to300MHz
PLLs have been developed as phase locked loops in a variety of applications.
The PLL generates 60~300MHz clock referenced at 8~20MHz.
The output clock frequency is selected by the resister M, N
“FOUT = FIN/M*N”
KC022H1007 | 2019-11-19
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PLL 60to300MHz
The PLL have been developed as phase locked loops in a variety of applications. This PLL generates 60~300MHz clock referenced at 8~20MHz. The output clock frequency is selected by the resister M, N
“FOUT = FIN/M*N”
KC022H0959 | 2018-11-26