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Interface
  • 기업 IP
  • 대학·연구소 IP
  • N관련된 신규용역가능
  • M수정/가공 판매가능
  • T기술지원 가능
  • P현 상태로만 판매가능
total: 92/862 IP Cores
    • 기업 IP
    • N
    • M
    • T

    HDMI 2.1/DisplayPort 1.4a Combo Transmitter PHY

    The SPPHHTG2S08 is the HDMI 2.1/DisplayPort 1.4a transmitter PHY. It is a companion PHY IP for the SPLOHTG2 HDMI 2.1/DisplayPort 1.4a transmitter controller IP or third-party controller IP. Its registers are recommended to be accessed from the controller IP or the interposer IP from the SOC through Alphasolutions' prop..

    KC3726H1098 | 2021-11-03

    • 기업 IP
    • P

    LPDDR5 16bit analog PHY Hard IP

    - LPDDR5 analog PHY hard IP satisfying JESD209-5_3

    KC024H1094 | 2021-10-05

    • 기업 IP
    • P

    SPDIF Rx Decoder

    The SPDIF Rx supports digital audio input. SPDIF Rx is a digital audio interconnect used in consumer audio equipment over relatively short distances. The signal is transmitted over either a coaxial cable with RCA connectors or a fiber optic cable with TOSLINK connectors. SPDIF interconnects components in home theaters ..

    KC3735S1087 | 2021-09-01

    • 기업 IP
    • N
    • M
    • T

    MIPI D-PHY RX

    This DPHY-RX is a high-frequency low-power, low-cost, source- synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, The High-Speed signals have a low voltage swing, while Low-Power signals have lar..

    KC567H1085 | 2021-07-20

    • 기업 IP
    • M

    Low power 8Gbps SerDes

    SerDes with 8.0Gbps data rate consists of 32-to-1 serializer, 1-to-32 de-serializer, and PLL with LC-VCO. This IP adopts an asynchronous system with embedded clock in serial data, and its IO interface uses a CML type. For BER test verification, loop back path and feed-forward path were inserted in IP and its function w..

    KC587H1055 | 2020-12-15