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  • 기업 IP
  • 대학·연구소 IP
  • N관련된 신규용역가능
  • M수정/가공 판매가능
  • T기술지원 가능
  • P현 상태로만 판매가능
total: 5/812 IP Cores
    • 기업 IP
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    FM_DAB_Tuner

    The dual-band DAB(Band-III and L-Band) and FM are integrated with RF Tuner through the low-power CMOS process technology. The RF tuner integrates three programmable gain LNAs, down conversion mixers, a channel selection filter, IF programmable gain amplifiers, a fractional-N frequency synthesizer with onchip VCO,..

    KC193H0852 | 2017-02-09

    • 대학·연구소 IP
    • T

    Gbps-level Wireless Video Data Transmission Demodulator (PHY&MAC) IP

    To realize the real-time transmission of the UHD-level (including HD-level), the Gbps-level data transmission should be obtained. In addition, for a seamless transmission of a high quality video, differentiated transmission schemes should be provided according to the characteristics of the video data. A wireless video..

    KU125S0604 | 2014-11-21

    • 대학·연구소 IP
    • T

    Gbps-level Wireless Video Data Transmission Modulator (PHY&MAC) IP

    To realize the real-time transmission of the UHD-level (including HD-level), the Gbps-level data transmission should be obtained. In addition, for a seamless transmission of a high quality video, differentiated transmission schemes should be provided according to the characteristics of the video data. A wireless video..

    KU125S0603 | 2014-11-21

    • 대학·연구소 IP
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    VHF/UHF Transceiver

    A 54~862MHz single-chip CMOS transceiver with a single LC voltage-controlled oscillator (VCO) fractional-synthesizer is developed for TV-band white-space communications and cognitive radio applications. The transceiver is based on a single conversion zero-IF architecture with integrated harmonic filtering capability. A..

    KU201H0422 | 2013-10-08

    • 대학·연구소 IP
    • N
    • M
    • T

    13.75GS/s FFT/IFFT processor

    This IP is a novel eight-parallel 128/256-point mixed-radix multi-path delay commutator (MRMDC) FFT/IFFT processor for high-speed OFDM systems such as UWB, WiMAX, and O-OFDM. The processor can reduce the number of complex multipliers from 11 to 2 at the second stage. Moreover, the processor can achieve a high throughp..

    KU248S0421 | 2013-10-04