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  • 기업 IP
  • 대학·연구소 IP
  • N관련된 신규용역가능
  • M수정/가공 판매가능
  • T기술지원 가능
  • P현 상태로만 판매가능
total: 14/877 IP Cores
    • 기업 IP
    • N
    • M
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    BCD1370_PLL

    It was designed using Samsung Foundry's BCD1370 process. PLLs have been developed as phase locked loops in a variety of applications. The PLL generates 60~180MHz clock referenced at 8~20MHz. The output clock frequency is selected by the resister P, M, S PLL output frequency PLLOUT = FIN / Pdiv_val * Mdiv_val / Sdiv..

    KC022H1150 | 2022-09-21

    • 기업 IP
    • M
    • T

    PLL 60to300MHz

    PLLs have been developed as phase locked loops in a variety of applications. The PLL generates 60~300MHz clock referenced at 8~20MHz. The output clock frequency is selected by the resister M, N “FOUT = FIN/M*N”

    KC022H1007 | 2019-11-19

    • 기업 IP
    • M

    PLL 60to300MHz

    The PLL have been developed as phase locked loops in a variety of applications. This PLL generates 60~300MHz clock referenced at 8~20MHz. The output clock frequency is selected by the resister M, N “FOUT = FIN/M*N”

    KC022H0959 | 2018-11-26

    • 대학·연구소 IP
    • P

    Analog PLL

    This 100MHz&125MHz PLL allows implementation of integer-N frequency synthesizers when used with an internal loop filter and external reference frequency. It is designed in 130nm BCDMOS technology for automotive applications and consists of phase and frequency detector(PFD), charge pump(CP), analog loop filter, voltage..

    KU335H0836 | 2016-10-14

    • 대학·연구소 IP
    • T

    PLL_Frequency Synthesizer

    For digital signal processing, frequency synthesizer is required to generate desired clock. A frequency synthesizer is an electronic circuit to generate some range of frequency. Frequency synthesizer is used in many case of digital circuit scheme. For example, DVFS that controls the frequency of the system clock to inc..

    KU462H0770 | 2016-04-18