A 10b 10MS/s 0.26mm2 2.3mW 0.11um CMOS SAR ADC
10-bit 10MS/s low-power SAR (successive-approximation register) ADC
A 10b 50MS/s 0.23mm2 17.5mW 90nm CMOS ADC
10-bit 50MS/s pipeline ADC
10bit 100M ADC
This IP is an analog-to-digital converter (ADC) employing a pipelined successive
approximation register (SAR) architecture for low power consumption and small
The proposed IP includes an internal clock generator, a reference buffer and a
current generator. The ADC is operated single clock at 1.0V supply and p..
9bit 12Msps ADC
This ADC is low power analog-to-digital converter (ADC) IP.
The IP architecture is robust and can be ported to other 130nm or 180nm processes. The ADC uses fully single pipeline architecture with custom low-disturbance. Digital error correction technique
The IP is implemented in EHV 162nm UMC process.
This makes ..
10bit 50MHz SAR ADC
This design is for analog to digital converter for 50MHz sampling speed. It adapts pipeline and Successive Approximate Register merged structure to provide a better performance. And also contain small calibration circuit to adjust the comparator offset caused by process variation. By using proposed Digital to Analog Co..